The speed, power, and complexity of integrated circuits, such as microprocessor chips, random access memory (RAM) chips, application specific integrated circuit (ASIC) chips, and the like, have increased dramatically in the last twenty years. More recently, these increases have led to development of so-called system-on-a-chip (SoC) devices. A SoC device allows nearly all of the components of a complex system, such as a cell phone or a television receiver, to be integrated onto a single piece of silicon. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
A key component in many highly integrated circuits, including SoC devices, is the field programmable gate array (FPGA). FPGA circuits are a particular class of general purpose integrated circuits (ICs) that can be configured (i.e., programmed) to perform a wide range of tasks. There are a number of different types of FPGA circuit topologies, including symmetrical array, row-based, sea-of-gates, and hierarchical programmable logic device (PLD). Each of these FPGA types has certain advantages over other types, depending on the specific application.
FPGA circuits generally are implemented using one of four technologies: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. In static RAM technology, programmable connections in the FPGA are made using pass transistors, transmission gates, or multiplexers controlled by a static random access memory (RAM) cell. Static RAM cells technology allow fast reconfiguration of a FPGA circuit. Anti-fuse technology uses an anti-fuse that is initially a high-impedance connection path (i.e., open circuit). The anti-fuse is then programmed into a low impedance (i.e., short circuit) or fused state. While anti-fuse technology is simple and less expensive than static RAM technology, an anti-fuse is a “program once” device. EPROM and EEPROM technologies use the same methods that are used in EPROM memories.
There are three primary configurable elements in a FPGA circuit: configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs) programmable logic devices (PLDs), and the like. A programmable interconnect generally connects a single output of a CLB to an input of another CLB. An interconnect comprises metal wires and transistors that act as pass gates and signal buffers that preserve the signal integrity. Control of the interconnect transistors may be provided by an SRAM cell, a flash RAM cell, or external pins. The programming of an interconnect is usually done in a static fashion, such as at the power-up of a stand-alone FPGA circuit, especially for flash RAM and SRAM based configurations. The I/O blocks provide the interface between the external pins of the IC package and the internal signals lines, including the programmable interconnects.
Despite the considerable advancements made in field programmable gate array-circuits, however, there remains room for improvement. There is a limitation to the complexity of the logic functions that may be implemented in a FPGA circuit of a particular size and density. More complex functions call for still greater FPGA density. However, this greater density must be achieved without incurring larger latencies due to increased propagation times through the FPGA circuit.
Therefore, there is a need in the art for system-on-a-chip (SoC) devices and other large scale integrated circuits that implement improved field programmable gate array (FPGA) circuits. In particular, there is a need for FPGA circuits, including embedded FPGA circuits, that achieve greater density and/or utilization over standard FPGA technologies. More particularly, there is a need for improved FPGA circuits that are capable of performing more complex logical functions while minimizing propagation times.